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Analog-to-digital converter (ADC)
Figure 25. Single ADC block diagram
Interrupt
RM0008
Flags
enable bit s
End of conversion
End of injected conversion
Analog watchdog even t
EOC
JEOC
AWD
EOCIE
JEOCIE
AWDIE
Analog
watchdog
ADC Interrupt to NVIC
Compare Result
High Threshold (12 bits)
Low Threshold (12 bits)
V REF+
Injected data registers
(4 x 16 bits)
V REF-
Regular data register
V DDA
(16 bits)
V SSA
Analog
DMA request
MUX
ADCx_IN0
ADCx_IN1
ADCx_IN15
GPIO
Ports
up to 4
up to 16
Injected
channels
Regular
channels
Analog to digital
converter
ADCCLK
Temp. sensor
V REFINT
JEXTSEL[2:0] bits
TIM1_TRGO
From ADC prescaler
TIM1_CH4
TIM2_TRGO
TIM2_CH1
TIM3_CH4
TIM4_TRGO
JEXTRIG
bit
Start trigger
(injected group)
EXTI_15
TIM8_CH4 (2)
JEXTSEL[2:0] bits
ADCx-ETRGINJ_REMAP bit
EXTSEL[2:0] bits
TIM1_CH1
EXTRIG
bit
TIM1_TRGO
TIM1_CH4
TIM4_CH3
TIM8_CH2
TIM8_CH4
TIM5_TRGO
TIM5_CH4
JEXTRIG
bit
Start trigger
(injected group)
TIM1_CH2
TIM1_CH3
TIM2_CH2
TIM3_TRGO
TIM4_CH4
Start trigger
(regular group)
TIM3_CH1
TIM2_CH3
TIM1_CH3
EXTSEL[2:0] bits
EXTRIG
bit
TIM8_TRGO
EXTI_11
(2)
TIM8_CH1
TIM8_TRGO
TIM5_CH1
Start trigger
(regular group)
TIM5_CH3
ADCx_ETRGREG_REMAP bit
Triggers for ADC3 (1)
ai14802d
1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2.
2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density products.
200/995
Doc ID 13902 Rev 9
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